Fifo error when trying to put input into Nios II Core

Hi I am trying to generate a signal and then output it to a computer.

I have generatered the signal no problem.

I have transferred data (not the signal) , using the Nios II core to the pc using ethernet no problem.

I want to buffer my signal before I put into the Nios II so I have used a fifo. but when I place the output of the fifo into the nios I get this error....

Error: WYSIWYG primitive "fifo_vhdl:inst19|scfifo:scfifo_component|scfifo_ov71:auto_generated|a_dpfifo_v581:dpfifo|dpram_n261:FIFOram|altsyncram_g2m1:altsyncram1|ram_block2a13" has mismatched parameters for port Port A, Data In

I have even tried just sending it tot he DAC and still same error.

Any ideas?

Below is also a copy of my .bsf

Thank you in advance for your help.