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Altera_Forum
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17 years ago

FIFO Depth

Hi All, I have a design issue. I want to knwo the efficient fifo depth. My write speed is 50 Mhz@16 bits, and read speed is 1bit@500 Mhz. Current;y i am validating in Altera FPGA and...
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Altera_Forum
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17 years ago

Hi Kaz,

Agreed. I referenced the document purely for info (and to be honest I didn't read it in that much detail!)

the doc does mention

--- Quote Start ---

In order to know the data rate of write operation, we need to know Number of data in a Burst which we have assumed to be B.

--- Quote End ---

So you're right, what is the magic number B?

In System sizing is definitely the way to go. Make an over estimate and monitor the fill level in a real situation.

Apologies if I have caused confusion