Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

FIFO Depth

Hi All, I have a design issue. I want to knwo the efficient fifo depth. My write speed is 50 Mhz@16 bits, and read speed is 1bit@500 Mhz. Current;y i am validating in Altera FPGA and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi vernmid,

With full respect I don't quite see how this math is going to be practically useful. It depends entirely on (B) defined as number of bits per burst(worst case). It ignores the spacing between bursts. It may suit a well spaced case.

But for a truely bursty input, I see no substitute for in-system sizing. I don't know of any reliable method to quantify burstiness