Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorFIFO Depth
Hi All, I have a design issue. I want to knwo the efficient fifo depth. My write speed is 50 Mhz@16 bits, and read speed is 1bit@500 Mhz. Current;y i am validating in Altera FPGA and...
Altera_ForumHonored Contributor
Honored ContributorYou effectively didn't specify your application. Thus it's impossible to give specific suggestions.
Missing points are e.g.: available methods of dataflow control for both interfaces, transfer sizes in block transfer, which side is initiating the transfer. It may be the case, that you aren't yet aware of these questions to exist. But we can't give the answer. As another point, the 500 MBit/s interface apparently involves a serializer.
