Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

FIFO Depth

Hi All, I have a design issue. I want to knwo the efficient fifo depth. My write speed is 50 Mhz@16 bits, and read speed is 1bit@500 Mhz. Current;y i am validating in Altera FPGA and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

50MHz * 16 bit gives a write bandwidth of 800MBit/s

500MHz * 1 bit gives a read bandwidth of 500Mbit/s

So it looks like your write bandwidth is greater than your read bandwidth? No FIFO can help here :)

I assume your input rate is not constant i.e. 16 bits of data are not written on every 500MHz clock.

This is the key to sizing FIFOs. What is the profile of your input data? i.e. how bursty is it?

(Short bursts of data can be absorbed by small FIFOs. longer bursts by larger FIFOs)

If you could define your input and output data in a bit more detail then forum uses may be able to offer sizing advice

Hope this helps