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Honored ContributorFatal error modelsim code 9 simulating 4 registers os 16bits each
Hi every one,
Why every day it pass I get more strange errors?!?!?! This time my problem is not with Quartus, is with modelsim. I'm trying to do a simple module for calculating the correlation of a signal X=R+I, but I get stucked with the buffer, Quartus compiles perfect with some warnings, but then Modelsim break out with code 9 trying to simulate 140Mbytes?? I have 4GB of RAM!!!, I dont understand what is happening. Next to this I put my code, the errors and a Process administrator image. TB_Correlator.vhd
--
--
library ieee;
use ieee.std_logic_signed.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
library STD;
use STD.textio.all;
--package mytypes is
-- type data_ram_in is array(3 downto 0) of std_logic_vector (15 downto 0);
-- type data_ram_out is array(3 downto 0) of std_logic_vector (31 downto 0);
--end package mytypes;
library altera;
use altera.all;
use work.all;
library ieee;
use ieee.std_logic_signed.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
library STD;
use STD.textio.all;
use work.mytypes;
entity TB_Correlator is
end TB_Correlator;
architecture TB of TB_Correlator is
component Correlator is
port(
CLOCK_50 :in std_logic;
SW : in std_logic_vector (17 downto 0);
LEDR : out std_logic_vector (17 downto 0)
);
end component;
signal CLOCK_50 : std_logic := '0';
constant PERIOD_50 : time := 20ns;
signal reset : std_logic :='0';
signal Data_in : std_logic_vector (15 downto 0):= (others=>'0');
signal Data_new: std_logic := '0';
begin
UUT: Correlator
port map(
CLOCK_50 =>CLOCK_50,
SW(17) => reset,
SW(15 downto 0) => Data_in,
SW(16)=>Data_new
);
gen_clock : process
begin
CLOCK_50 <= not CLOCK_50 after PERIOD_50/2;
end process;
reset_ini: process
begin
reset<='1';
wait for PERIOD_50;
reset<='0';
wait;
end process;
datos : process
begin
wait for PERIOD_50*10;
Data_in <= std_logic_vector(to_signed(1,16));
Data_new <= '1';
wait for PERIOD_50;
Data_new <= '0';
wait for PERIOD_50*10;
Data_in <= std_logic_vector(to_signed(9,16));
Data_new <= '1';
wait for PERIOD_50;
Data_new <= '0';
wait for PERIOD_50*10;
Data_in <= std_logic_vector(to_signed(12,16));
Data_new <= '1';
wait for PERIOD_50;
Data_new <= '0';
wait for PERIOD_50*10;
Data_in <= std_logic_vector(to_signed(12,16));
Data_new <= '1';
wait for PERIOD_50;
Data_new <= '0';
wait for PERIOD_50*10;
Data_in <= std_logic_vector(to_signed(75,16));
Data_new <= '1';
wait for PERIOD_50;
Data_new <= '0';
wait for PERIOD_50*10;
Data_in <= std_logic_vector(to_signed(37,16));
Data_new <= '1';
wait for PERIOD_50;
Data_new <= '0';
wait for PERIOD_50*10;
Data_in <= std_logic_vector(to_signed(31,16));
Data_new <= '1';
wait for PERIOD_50;
Data_new <= '0';
wait for PERIOD_50*10;
Data_in <= std_logic_vector(to_signed(-9,16));
Data_new <= '1';
wait for PERIOD_50;
Data_new <= '0';
wait for PERIOD_50*10;
wait;
end process;
end TB;
-------------------------------------
-- Instrumentacion - DSP
--
-- DE2-115
-- Project: Correlator
--
-- Guillermo Loustau
--
--
-------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
package mytypes is
type data_ram_in is array(3 downto 0) of std_logic_vector (15 downto 0);
type data_ram_out is array(3 downto 0) of std_logic_vector (31 downto 0);
end package mytypes;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
use work.mytypes;
entity Correlator is
port(
CLOCK_50 :in std_logic;
SW : in std_logic_vector (17 downto 0);
LEDR : out std_logic_vector (17 downto 0)
);
end Correlator;
architecture beh of Correlator is
component bufer is
port(
clk :in std_logic;
reset :in std_logic;
buf_en :in std_logic;
Data_in :in std_logic_vector(15 downto 0);
Data_array :out work.mytypes.data_ram_in;
Data_out :out std_logic_vector(15 downto 0)
);
end component;
component mult is
port(
clk :in std_logic;
reset :in std_logic;
mult_en :in std_logic;
Data_a :in work.mytypes.data_ram_in;
Data_b :in work.mytypes.data_ram_in;
Data_out :in work.mytypes.data_ram_out
);
end component;
signal buf_mult_a : work.mytypes.data_ram_in;
signal Data_in,buf_buf_a,buf_a_end : std_logic_vector(15 downto 0);
signal buf_en : std_logic := '1';
signal reset : std_logic;
begin
bufer_a1_Map : bufer port map (
CLOCK_50,reset,
buf_en,
Data_in,buf_mult_a,buf_buf_a
);
bufer_a2_Map : bufer port map (
CLOCK_50,reset,
buf_en,
buf_buf_a,buf_mult_a,buf_a_end
);
reset <= SW(17);
Data_in <= SW (15 downto 0);
LEDR <= b"00" & buf_a_end;
buf_en <= SW(16);
end beh;
-------------------------------------
-- Instrumentacion - DSP
--
-- DE2-115
-- Project: Correlator
-- Buffer Array "Circular"
-- Guillermo Loustau
--
--
-------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
use work.mytypes;
--package mytypes is
-- type data_ram_in is array(3 downto 0) of std_logic_vector (15 downto 0);
-- type data_ram_out is array(3 downto 0) of std_logic_vector (31 downto 0);
--end package mytypes;
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.std_logic_signed.all;
--use ieee.numeric_std.all;
entity bufer is
port(
clk :in std_logic;
reset :in std_logic;
buf_en :in std_logic;
Data_in :in std_logic_vector(15 downto 0);
Data_array :out work.mytypes.data_ram_in;
Data_out :out std_logic_vector(15 downto 0)
);
end bufer;
architecture beh of bufer is
signal bufer_circ : work.mytypes.data_ram_in;
begin
Data_array <= bufer_circ;
process (clk)
variable i : integer range 0 to 3;
begin
if(rising_edge(clk))then
if(buf_en = '1') then
for i in 0 to 4 loop
if(i = 4) then
bufer_circ(i-1) <= Data_in;
elsif ( i = 0 ) then
Data_out <= bufer_circ(i);
else
bufer_circ(i-1)<= bufer_circ(i);
end if;
end loop;
end if;
end if;
end process;
end beh;
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run 1 ms
# ** Fatal: (vsim-4) ****** Memory allocation failure. *****
# Attempting to allocate 131072 bytes
# Please check your system for available memory and swap space.
# ** Fatal: (vsim-4) ****** Memory allocation failure. *****
# Attempting to allocate 131072 bytes
# Please check your system for available memory and swap space.
