Fast IO register constraints won't apply

Hi,

I have a SRAM memory interface in my design and I registered all the signals in a component called mem_ctrl. I set these registers as fast input/output registers in assignment editor. But I got a bounch of warnings like the following:

Warning: Can't pack node "mem_ctrl:COMP_MEM_CTRL|addr[0][0]" and I/O cell a_tap[0]. The node and I/O cell are connected across a Design Partition boundary.

And it takes almost 6.5ns for a signal going from its register to the pin according to the timing analyzer.

Should I put all those registers in the top level to apply fast IO register constraints? Or is there anything else I should pay attention to? (the mem_ctrl component is in the top partition, and I don't understand why the message said the signal needs to across partition boundary).

Your help is very much appreciated.

Hua