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Altera_Forum's avatar
Altera_Forum
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17 years ago

Fast IO register constraints won't apply

Hi,

I have a SRAM memory interface in my design and I registered all the signals in a component called mem_ctrl. I set these registers as fast input/output registers in assignment editor. But I got a bounch of warnings like the following:

Warning: Can't pack node "mem_ctrl:COMP_MEM_CTRL|addr[0][0]" and I/O cell a_tap[0]. The node and I/O cell are connected across a Design Partition boundary.

And it takes almost 6.5ns for a signal going from its register to the pin according to the timing analyzer.

Should I put all those registers in the top level to apply fast IO register constraints? Or is there anything else I should pay attention to? (the mem_ctrl component is in the top partition, and I don't understand why the message said the signal needs to across partition boundary).

Your help is very much appreciated.

Hua

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Have you applied the constraint to the pin of the top level or a signal lower down the hierarchy?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    Have you applied the constraint to the pin of the top level or a signal lower down the hierarchy?

    --- Quote End ---

    Actually, I applied the constraints to both the pin and the register (in the component). Both of them got the warning message.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The constraint should be applied to the register, not to the pin, I think. At least I've been using the constraint succesfully in this way.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Applying to the pin shouldn't create this problem, should it? I will take it out anyway.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    Warning: Can't pack node "mem_ctrl:COMP_MEM_CTRL|addr[0][0]" and I/O cell a_tap[0]. The node and I/O cell are connected across a Design Partition boundary.

    (the mem_ctrl component is in the top partition, and I don't understand why the message said the signal needs to across partition boundary).

    --- Quote End ---

    It actually means the opposite. Because of the register packing and fast I/O assigment, they can't cross a partition.

    Left click on the warning message and select "Help". Quartus will show a more detailed description of the warning, and will also point you to the relevant Handbook chapter that elaborates about the issue.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I know what you are saying, but what I meant was:

    The mem_ctrl module is in the top partition, so the signal doesn't cross any partition boundary. I don't understand why the software think the node and the IO cell are connected across a Design Partition boundary.

    Thanks anyway.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    The mem_ctrl module is in the top partition, so the signal doesn't cross any partition boundary. I don't understand why the software think the node and the IO cell are connected across a Design Partition boundary.

    --- Quote End ---

    Again, please read the relevant handbook chapter pointed at the warning message help.

    There are other reasons that might provoke this warning. e.g, the output enable of the signal can't cross a paritition boundary. Tapping might also restrict register packing.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks vjAlter, I have read those chapters before I came here ...

    After tried a few things, it seems that moving those registers from mem_ctrl module to the top level did help... verifying this right now.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    Thanks vjAlter, I have read those chapters before I came here ...

    --- Quote End ---

    Ok. Sorry about insisting on that.

    My point was to make sure you understand all the restriction on I/O register packing when using incremental compilation. And also that, as explained there, the message sometimes is misleading, and might be provoked by other restrictions, not exactly because the node and I/O cell are on different partitions.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    None taken, vjAlter.

    And yes, moving those registers to the top level did the trick. The register node and the IO buffer are in the same cell now.