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Thank you zoomkrupesh. After setting up an additional PLL for signaltap with frequency that is twice as fast as the working frequency, I had a setup violation on a path from a node in my design to a node in signaltap module.
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You can assign false path between signal tap sampling clock and your design clock.
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I'm not sure why there's clock domain crossing here since my understanding is that the second, faster clock is for signaltap sampling only and does not interfere the main module. Any suggestion?
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Off course there will be clock domain crossing between signal tap clock and your design clock.Whatever node or signals you add in your signal tap file is generated on your design clock which is sampled by signal tap clock.
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