Forum Discussion
seanw_skhms
Occasional Contributor
Occasional ContributorFailed to closure timing in building the "pcie-gen4" example in Agilex F-Series FPGA Installer pkg
I am trying to build the "pcie_gen4" example design provided in the "Intel Agilex F-Series FPGA Installer Package, ES-3V", which I downloaded from https://www.intel.com/content/www/us/en/programmable...
Sorry, I was wrong. Actually, the timing error is located in the mm_interconnect modules which are auto inserted by the tool. I missed the parameter settings in the original design for these interconnect modules. After I corrected the pipe-stage parameter setting in these interconnect modules, The routing timing error is fixed.
SengKok_L_Intel
Regular Contributor
Regular ContributorThank you for the update, and this is glad to see the problem is resolved.
Just for your information, for the PCIe P tile example design, you can also generate it from the PCIe IP GUI, and it is timing clean. Thanks.
Regards -SK
