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seanw_skhms's avatar
seanw_skhms
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

failed in creating agilex-f p-tile-pcie-avmm (RP X4) design example

Quartus prime version 20.2.0 build 50 06/11/2020 SC pro edition, free 30 day license. Following the instructions shown in section 5.3, "generating the design example", in the document of "Intel FP...
  • BoonT_Intel's avatar
    BoonT_Intel
    5 years ago

    Sorry, I overlook the dev kit setting. After putting the Agilex dev kit and generate the ED, the design files look bigger so I can't directly attach to here.

    Here is the step to get the file:

    Install Filezilla that can download from here:

    https://filezilla-project.org/download.php?type=client

    After installing, launch the tool and login as below:

    Host: secureftp.intel.com

    Username: tmp01481

    Password: W@ng1234

    Port 21.

    You can see the zip file is located at the right of the window. Name = wang_ag.zip.

BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hello Sir,

I open your latest attached. ip file and generate the example design from there. The generation is successful.

I believe the Agilex Example design (ED) is create based on the faster speed grade for now, so no matter what device that you set in your project, the example design will generate based on the device AGFB014R24A2E2VR0.

Just want to let you know that the support for Ptile PCIe IP in Agilex is still in prelim stage, thus it might not cover across all speed grade.

At this moment, do you want me to send you my generated example design so that you can use it directly without generation?

Also, are you mentioned that the “Current development kit” in your GUI is empty? From my side, I can see “none”, “S10 DX” and “Agilex”.

  • BoonT_Intel's avatar
    BoonT_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    By the way, are you able to generate the standalone IP? Also do you try to generate other IP's ED?

    • seanw_skhms's avatar
      seanw_skhms
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      I am new in using the Quartus tool and the first practice is to generate the PCIe RP IP. So I have not do any other IP-DE yet.

      regards,
      Xiao

      • seanw_skhms's avatar
        seanw_skhms
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        I think the example design generation failure is caused by a bug in adding in the module of clock_crossing_bridge. The error message, at line#40 shown in "received_error_2.log" attached previously, shows,

        Error: add_fileset_file: No such file C:/Users/PC_LAB_FPGA1/AppData/Local/Temp/alt8499_1907179446840489927.dir/0001_intel_pcie_ptile_avmm_0_gen/ip/pcie_ed/pcie_ed_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge_1920/synth/pcie_ed_clock_crossing_bridge_altera_avalon_mm_clock_crossing_bridge_1920_fdcxukq.v/pcie_ed_clock_crossing_bridge_altera_avalon_mm_clock_crossing_bridge_1920_fdcxukq.v

        The file name of "pcie_ed_clock_crossing_bridge_altera_avalon_mm_clock_crossing_bridge_1920_fdcxukq.v" is inserted two times in the file searching path.

        (But the message at line#38-39 shows that the other two rtl files, "*dc_fifo_1920_qcx4w5q.*", in the same folder were fetched correctly.)

        regards,
        Xiao

  • seanw_skhms's avatar
    seanw_skhms
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    In the "IP Parameter Editor Pro" window, when I clicking the "Generate HDL ..." control button located at bottom-right corner, the generation is always successful no matter of the "Enable PHY Reconfiguration" selection. But when clicking the "Generate Example Design ..." control, the generation are always failed no matter of the "Enable PHY Reconfiguration", or the "Current development kit" or the "Design Environment" (standalone/system) selections.

    The Agilex F-series development kit, intel PN# DK-DEV-AGF014E3ES we purchased, has the device of AGFB014R242E3VR0 installed. The current released version of Quartus tool has to be able to support it. I saw the log message shows that the generation uses AGFB014R242E3VR0 sometimes, but not always. I saw the both of AGFB014R242E3VR0 and AGFB014R242E2VR0 devices are listed in the *.ip file, which looks not right for me.

    I am able to see the "none, stratix, agilex" options in the "Current development kit" control, and I set to use the agilex developemnt kit. I saw your log message, "ptile_generated.txt", shows that the generation is targeting to Stratix 10 development kit, but the device is AGFB014R242E2VR0, which looks so wrong for me. I made a test by selecting the Stratix 10 development kit, the log message shows that the tool changed the device to 1SD280PT2F55E2VGS1.

    If I open the "Device Family" window, the device setting shows the right values of "Agilex" and "AGFB014R242E3VR0". but why the "Stratix 10" development kit still shows up in the generating option?

    The "Current development kit" has the "Agilex F-Series" development kit option, but I do not see how and where this board is set in the tool. When following the document ug-20268, section 5.3 to run the "file->new project wizard", in the "family, device & board" setting page, the "board" tab is empty. I believe the Agilex-F development board should be shown here, but I could not find out how to add it in.

    Could you please help to generate a RP IP with example design for me by using the following settings,

    family : Agilex

    device : AGFB014R242E3VR0

    development kit : Agilex F-Series

    IP : intel-pcie-ptile-avmm

    Design environment : System

    Hard-IP mode : Gen4x4, interface - 128 bit

    Port-Mode : Root Port

    PLD Clock Frequency : 350 MHz

    Example Design Files are for Synthesis only in verilog format targeting to Agilex-F development kit.

    Then let me know how to download the whole design folder.

    Thanks,

    Xiao