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New Contributor

1 year ago

F-tile FHT 400GE lane swap

Hi！ we are using AGIB027R29A1E2VB FHT for 400GE-4. when we using （0,1,2,3）-> (0,1,2,3) FPGA design project receive an error ： QSFP112_RX0 -> FHTL12A_RX_CH0 QSFP112_RX1 -> FHTL12A_RX_CH1...

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ZiYing_Intel

Frequent Contributor

1 year ago

Hi,

The order of channel naming is reversed order of streams in Ethernet HIP block. For further information, you can refer to link below, section F-tile Architecture, https://www.intel.com/content/www/us/en/docs/programmable/683872/24-1-4-8-0/f-tile-architecture.html

Best regards,

zying

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F-tile FHT 400GE lane swap

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