Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Externally clocking ALTLVDS with a large number of channels

I'm attempting to fit a 29 channel ALTLVDS clocked by an external PLL into a EP4SGX70HF35C2 Stratix IV. I get the following error from the fitter: "Error (176143): Project contains fast PLL driving 2...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Sorry for the confusion. The DAC (AD9739A) provides a clock that I'm feeding to the PLL. However, you also provide a DDR clock in sync with the data back to the DAC. I was using the "Transmitter outclock" in ALTLVDS Transmitter Settings to generate this clock. So I specified 28 channels in MegaWizard, but it needs 29 transmitters, and I assumed the 29th is for the clock.