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Altera_Forum
Honored Contributor
Honored ContributorExternally clocking ALTLVDS with a large number of channels
I'm attempting to fit a 29 channel ALTLVDS clocked by an external PLL into a EP4SGX70HF35C2 Stratix IV. I get the following error from the fitter: "Error (176143): Project contains fast PLL driving 2...
Altera_ForumHonored Contributor
Honored ContributorIn altlvds, did you say 28 channels or 29? I thought the clock was a separate LVDS input driving the PLL, and you'd be able to get 29 data channels?
