External PHY RMII timing

Hi everyone,

I have an external PHY connected to the FPGA via RMII. In the FPGA I convert the RMII signals to MII using a converter module and then it is conected to the transceiver (PCS). The external PHY and the RMII converter in the FPGA are both clocked using a common external 50 MHz clock. I am testing the design at the moment and about 0.1% of the frames are discarded due to bit error (CRC errors). I am thinking it could be related to timing problems; either wrong timing constraints or due to clock domain crossing problems. Here are my timing constraints:

http://www.alteraforum.com/forum/attachment.php?attachmentid=11604&stc=1

create_clock -name clkA-period "50 MHz" [get_ports {clkA}]

create_clock -name virt_clkA -period "50 MHz"

set_clock_groups -asynchronous

-group [get_clocks clkA]

set_input_delay -clock virt_clkA -max [expr $CLKBd_max + $phy_tco_max + $BDa_max - $CLKAd_fpga] [get_ports {phy*_rx*}]

set_input_delay -clock virt_clkA -min [expr $CLKBd_min + $phy_tco_min + $BDa_min - $CLKAd_fpga] [get_ports {phy*_rx*}]

set_output_delay -clock virt_clkA -max [expr $CLKAd + $BDa_max + $phy_tsu - $CLKBd_min] [get_ports {phy*_tx*}]

set_output_delay -clock virt_clkA -min [expr $CLKAd + $BDa_min - $phy_th - $CLKBd_max] [get_ports {phy*_tx*}]

CLKBd : delay of clock to phy

BDa : Board delay

CLKAd : delay of clock to FPGA

I would appreciate it if someone could tell me if the timing constraints are correct and if they are enough or I missed something.

Thanks a lot.