External Memory Interfacing in the Cyclone V SoCKIt

Hello,

Has anyone worked with the DDR3 Hard Memory Controller of the Cyclone V SocKit board (http://rocketboards.org/foswiki/view/documentation/arrowsockitevaluationboard) using the External memory interfacing IP with UNIPHY? I would like to write a small user logic block to talk to the external memory. The examples in the altera handbook only have the traffic generator and example design that the IP core generates does not work.

Particular question: as both the Memory Interface IP and the JTAG master are Avalon MM mapped, I am not able to use the system console to talk to the memory using the attached Qsys file. I'll be thankful for help. The one in the picture is the soft controller with UNIPHY though

Thanks!