Example project for Arria II GX dev kit

I'm successfully implement a DDR2 and DDR3 memories and some pripherials in one project.

So, at now i try to add TSE_MAC in project. And i have problems.

The tse modules connections is typically as other many projects. FPGA project compiles succesfully. Nios project also successfully compiles.

But when i load project on board, then NIOS console show it:

 Inst & Data Cache Initialized.
 Setting up stack and global pointers.
 Clearing BSS 
 Calling alt_main.
 Entering alt_main, calling alt_irq_init.
 Done alt_irq_init, calling alt_os_init.
 Done OS Init, calling alt_sem_create.
 Calling alt_sys_init.

and stops the loading.

I research that app (ucos) stop at alt_sys_init.c:

void alt_sys_init( void )
{
    ALTERA_AVALON_TIMER_INIT ( HIGH_RES_TIMER, high_res_timer);
    ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer);
    ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart);
    ALTERA_AVALON_LCD_16207_INIT ( LCD, lcd);
    ALTERA_AVALON_PERFORMANCE_COUNTER_INIT ( PERFORMANCE_COUNTER, performance_counter);
    ALTERA_AVALON_SGDMA_INIT ( SGDMA_RX, sgdma_rx);
    ALTERA_AVALON_SGDMA_INIT ( SGDMA_TX, sgdma_tx);
    ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid);
    TRIPLE_SPEED_ETHERNET_INIT ( TSE_MAC, tse_mac);
}

at line altera_avalon_timer_init ( sys_clk_timer, sys_clk_timer);

So, the sys_clk_timer period sets to 10 ms. It more than needed for most projects. But it can't init the timer.......

Reset and Exception vectors are set to Oh-Cnip memory.

Why?

SOPC system attached:

http://www.alteraforum.com/forum/attachment.php?attachmentid=5811&stc=1&d=1335511668