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ochiang's avatar
ochiang
Icon for New Contributor rankNew Contributor
1 year ago

Ethernet suggestion

Hi, I am using a Cyclone V SoC FPGA and I would like to inquire about the feasibility of using this component for Ethernet communication at speeds of at least 2.5Gbps. I am open to using either ...
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Jeet14's avatar
Jeet14
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi,


Yes, you need to write RTL logic for MAC+PCS & MDIO logic as well for external PHY's then you can directly connect it with XCVR Native PHY 2.5G.


Regards

Tiwari


  • ochiang's avatar
    ochiang
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi Tiwari,

    I am very grateful for your information; it has been very helpful to me.

    However, I have some additional questions. There is already a Standard PCS within the Native PHY. When I select GigE 2.5G, it sets up to enable PCS 8b/10b. How is this different from the PCS you mentioned? Specifically, what additional PCS functionality do I need to implement? Could you provide some hints?

    Are you referring to handling things like Ordered-sets?

    Thank you very much.