Honored Contributor
Honored ContributorIt isn't clear for me yet, i don't understand what is the differnce between to 'in' type either it is clk or inc, inc signal is high for just one clk cycle , and a process runs just when some changes accures in its sensitive list and in my code on just pos edge, exactly what we want to do when we use clk .
i think it should make a D flip-flop for that part that just works on pos edge on inc ( we can consider it as a clk). p.s: but i added a clk signal to my sensitive list to see am i right or not, and put the whole process in a if clause to run just when the clk has changes to high(red part) this is the whole code.. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.math_real; use ieee.std_logic_unsigned.all; entity dataPath is port(clk, reset, shift, add, inc, swap, comp:in std_logic; datain:in std_logic_vector(15 downto 0); dataout: out std_logic_vector(15 downto 0)); end dataPath; architecture computer of dataPath is signal accumulator:std_logic_vector(15 downto 0):= "0000000000000000"; begin dataout <= accumulator; process(clk, reset, shift, add, inc, swap, comp) begin if ( clk = '1') then if (reset = '1') then accumulator <= "0000000000000000"; else if (shift = '1') then accumulator <= '0' & accumulator(15 downto 1); else if (add = '1') then accumulator <= accumulator + datain; else if (inc = '1' ) then accumulator <= accumulator + 1; else if( swap = '1') then accumulator <= accumulator ( 7 downto 0) & accumulator( 15 downto 8); else accumulator <= accumulator; end if; end if; end if; end if; end if; end if; end process; end computer; --------------------------------------- library ieee; use ieee.std_logic_1164.all; entity controller is port(serialin, clk:in std_logic; reset, shift, add, inc, swap, comp: out std_logic); end controller; architecture ctr_states of controller is TYPE state is ( dummy, dummy1, dummy2, ready, ready1,ready2, ready3, ready4, ready5 , resetS, shiftS, addS, incS, swapS, compS); signal dummy_state, ready_state:std_logic; signal present_state:state:= dummy;signal next_state : state; begin --shayad bayad hazf she -- shift <= '0'; -- add <= '0'; -- inc <= '0'; -- swap <= '0'; -- comp <= '0'; PROCESS(clk) BEGIN if ((clk'EVENT) AND (clk = '1')) then present_state <= next_state; end if; END PROCESS; process( present_state, serialin ) begin case present_state is when dummy => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= dummy1; else next_state <= dummy; end if; when dummy1 => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= dummy2; else next_state <= dummy; end if; when dummy2 => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= ready; else next_state <= dummy; end if; when ready => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= ready3; else next_state <= ready1; end if; when ready1 => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= ready4; else next_state <= ready2; end if; when ready2 => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= shiftS; else next_state <= resetS; end if; when ready3 => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= ready; else next_state <= ready5; end if; when ready4 => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= incS; else next_state <= addS; end if; when ready5 => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= compS; else next_state <= swapS; end if; when resetS => reset <= '1'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= dummy1; else next_state <= dummy; end if; when shiftS => reset <= '0'; shift <= '1'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= dummy1; else next_state <= dummy; end if; when addS => reset <= '0'; shift <= '0'; add <= '1'; inc <= '0'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= dummy1; else next_state <= dummy; end if; when incS => reset <= '0'; shift <= '0'; add <= '0'; inc <= '1'; swap <= '0'; comp <= '0'; if (serialin = '1') then next_state <= dummy1; else next_state <= dummy; end if; when swapS => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '1'; comp <= '0'; if (serialin = '1') then next_state <= dummy1; else next_state <= dummy; end if; when compS => reset <= '0'; shift <= '0'; add <= '0'; inc <= '0'; swap <= '0'; comp <= '1'; if (serialin = '1') then next_state <= dummy1; else next_state <= dummy; end if; -- when others => -- reset <= '0'; -- shift <= '0'; -- add <= '0'; -- inc <= '0'; -- swap <= '0'; -- comp <= '0'; -- next_state <= dummy; end case; end process; end ctr_states;
