errors in quartus when simulation

Hi,

I don't quite follow you about ASIC, I wouldn't bother about that if I am doing FPGAs. If you are just testing leds with datan values then you get the test pattern(you only need clock and reset inputs)

Your code can be like this if you want safe design:

process(reset,clk)

begin

if (reset='0') then

ledn <= (others => '0');

datan <= (others => '0');

counter<=(others=>'0');

elsif (clk'event and clk='1') then

count <=count + 1; -- assuming modulo 2, no maximum defined

if(count(10) = '1')then -- divider

datan <= datan + 1;

end if;

case datan is

when "000" => ledn<="10000000";

when "001" => ledn<="00000001";

when "010" => ledn<="00000010";

when "011" => ledn<="00000100";

when "100" => ledn<="00001000";

when "101" => ledn<="00010000";

when "110" => ledn<="00100000";

when "111" => ledn<="01000000";

end case;

end if;

end process;

Notice that leds wouldn't show to the eye when fast changes occur. So you should be kind to the eye limitations. There will also be one clock latency in simulation between datan value and ledn value