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Altera_Forum
Honored Contributor
Honored Contributorerrors in quartus when simulation
I have some code about LEDs cycle. I wrote two process, one is a time divider, the other is LED turn on according with divider. the project was complied, but quartus has some errors when staring simu...
Altera_ForumHonored Contributor
Honored ContributorHi,
You are very nice teachers. I think that the second process always runs when counter(10) is '1', because the counter(10) is puted to the sensitivity list. I have corrected the code. the another hands, I'm reading the book about VHDL at afternoon. It said that combinatorial feedback is not admitted when designing ATPG(auto test pattern generation), so I must avoid to write this code such as q<=q+1 in my architecture? Could you give me some hint? You told me ASIC is usually used this method, but ASIC also needs testing in the manufacture. How does ASIC tesing without ATPG?
