errors in quartus when simulation

Hi,

You are very nice teachers.

I think that the second process always runs when counter(10) is '1', because the counter(10) is puted to the sensitivity list. I have corrected the code.

the another hands, I'm reading the book about VHDL at afternoon. It said that combinatorial feedback is not admitted when designing ATPG(auto test pattern generation), so I must avoid to write this code such as q<=q+1 in my architecture? Could you give me some hint?

You told me ASIC is usually used this method, but ASIC also needs testing in the manufacture. How does ASIC tesing without ATPG?