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Altera_Forum
Honored Contributor
Honored Contributorerrors in quartus when simulation
I have some code about LEDs cycle. I wrote two process, one is a time divider, the other is LED turn on according with divider. the project was complied, but quartus has some errors when staring simu...
Altera_ForumHonored Contributor
Honored ContributorHi,
As explained to you by Pletz. If you only depend on combinatorial delay to update then you will incrementing many times during one clock period and thats not what you want. Combinatorial feedback is not suitable for fpgas but is used in the ASICs e.g.for SR latch where two nand gates feedback to each other after controlled delay. Note also you may insert all assignments of second process in the first clocked process since you are inferring latches(if count(10) = '0' is not defined). You should avoid latches as well...
