Error using while converting code to VHDL

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I cannot open the file because I don't have the software, but I assume the names are all correct. If you have code, could you post that in a post instead of an attachment? What is connected to output port 1? Is this an array with a single element?

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@Pietr.Thanks for your reply.I have written the code in my post. In figure there are 4 blocka two i/n and one o/p block. The code above is written in function block the middle one.Can you check it please. here is code

x1=[1 2 3 4 5 6 7 8 9];

x2=[3 4 5 6 7 8 9 2 1];

n=length(x1);

xc=zeros(2*n-1,1);

for i=1:2*n-1

if(i>n)

j1=1;

k1=2*n-i;

j2=i-n+1;

k2=n;

else

j1=n-i+1;

k1=n;

j2=1;

k2=i;

end

xc(i)=sum(conj(x1(j1:k1)).*x2(j2:k2));

end

xc=flipud(xc);