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Altera_Forum's avatar
Altera_Forum
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10 years ago

Error using while converting code to VHDL

Dear All, I am trying to find delay between two signals using cross correlation on FPGA .Kindly can some one please help me how i can do that. Any link or any useful informati...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I cannot open the file because I don't have the software, but I assume the names are all correct. If you have code, could you post that in a post instead of an attachment? What is connected to output port 1? Is this an array with a single element?