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Altera_Forum
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13 years ago

error sopc builder

hi i have this error when i add my own component en verilog with an interface avalon Error: rtp_tx_0.ram_master: ddr_sdram.s1 (0x0..0x1ffffff) is outside the master's address range (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi

can you tell me how can i define the component port as a maser in details

thank you :)

??