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Altera_Forum's avatar
Altera_Forum
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12 years ago

error sopc builder

hi i have this error when i add my own component en verilog with an interface avalon Error: rtp_tx_0.ram_master: ddr_sdram.s1 (0x0..0x1ffffff) is outside the master's address range (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Your component exposes an Avalon master interface whose address port appears to be only 4 bit wide.

So it can't definitely drive the 25bit address range of the sdram slave port.

I think you are missing some point.

Two guesses:

- you defined the component port as a master, but it is actually a slave

- you failed to export address lines