error message: "can't verify device number 1"

Hello Dan,

I generally agree with your assumption that no other pins than power supply/ground and dedicated JTAG signals should play a role in JTAG configuration. Particularly bank 1 VCCIO and VCCINT are needed to operate the JTAG interface. There are some hints in the MAX II device handbook regarding possible JTAG problems, e.g. the possibility of temporary VCCINT droop due to current spikes during programming or the necessisty of having defined TCK and TMS levels during power up. Although I never had similar JTAG problems with any Altera device either CPLD or FPGA, I would expect something of this kind. Also bad solder joints as you mentioned may be possible cause, but less likely to my opinion.

Regards,

Frank