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NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Error during Schematic to VHDL conversion.

Hello, I used create/update option in Quartus 18.0 to generate a VHDL file from a schematic: It is a sign extension operation where MOD1_OUT[9] is extended to convert 10 bit vector to a 2...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

I'm not sure what you're doing there (it looks like a short circuit), but individual signals in the schematic editor must have the bit in square brackets: MOD1_OUT[9].

#iwork4intel

  • NShan12's avatar
    NShan12
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hello,

    I changed the name to MOD1_OUT[9] (with square brackets added) as shown below. But no change in the generated code.

    And this is not a short circuit. It is just extending the MSB of a 10 bit vector to generate a 21 bit vector output. But the VHDL code generated is concatenating the complete vector "MOD1_OUT_ALTERA_SYNTHESIZED" instead of concatenating only the 10th bit "MOD1_OUT_ALTERA_SYNTHESIZED(9)". I encountered similar issues in other schematic files as well.