Error compiling my project with the standard niosII_cycloneII_2C35

The DDR SDRAM controller should be directly driven by a clock coming into the FPGA. This is because hidden in the controller is a PLL that creates all the clocks it needs. So right now, you have an input clock going to the PLL in your sopc system and then going to another PLL in the DDR controller. This is probably the source of some of your errors.

Also, any modules in the sopc system that are triggered by different clocks should be divided by a clock crossing bridge. Your DDR SDRAM controller is going to have to be behind one of these clock bridges, then you'll be using the sys_clk that it generates to trigger the other modules around it.

Check out the "nios architect tutorial", or the ddr controller handbook or tutorial for more in-depth info.