Honored Contributor
Honored Contributornow t have this error:
info: ------------------------------------------------error: post compile timing analysis failed (retcode=1)
info: the most likely cause of this type of error is:
info: (1) some signals on the local-side interface are not connected causing logic to be optimised away,
info: this script requires that the complete logic for the specified width of the datapath (both read and write paths) be present in the design.
info: (2) the clear-text hdl files for the datapath may have been modified.
info: (3) not all clocks from the system pll are global.
extra info: speed grade c6 used for analysis
extra info: memory device can operate at 85.00 mhz with a lower cl than 2.5
info: in-system timing verification of ddr/ddr2-sdram megacore variation 'ddr_sdram_0' complete.
info: please run the appropriate script for in-system verification of other ddr/ddr2-sdram megacore variations you may have in your project, and check system fmax.
error: evaluation of tcl script auto_verify_ddr_timing.tcl unsuccessful
error: quartus ii shell was unsuccessful. 2 errors, 0 warnings
error: peak virtual memory: 72 megabytes
error: processing ended: mon may 03 08:31:38 2010
error: elapsed time: 00:00:31
error: total cpu time (on all processors): 00:00:01
error: quartus ii full compilation was unsuccessful. 4 errors, 830 warnings
