hi,
having the same problem recently, with maybe same flash parallel (256P30), it seems that nios2 sopc it not well connected to the flash :
CFI flash memory interface IP use 8-bit address when the 256P30 is a 16bits flash, even if we set Data width to 16bits in IP... So Address 0 should be forget and only A1..A24 out of sopc instantiation directly connected to flash pin in top module. like this in VHDL:
-- the_cfi_flash0
address_to_the_cfi_flash(24 downto 1) => FLASH_A(23 downto 0),
address_to_the_cfi_flash(0) => FLASH_A_NOT_USED,
data_to_and_from_the_cfi_flash => FLASH_D,
read_n_to_the_cfi_flash => FLASH_OE_N,
select_n_to_the_cfi_flash => FLASH_CE_N,
write_n_to_the_cfi_flash => FLASH_WE_N,
(and connect FLASH_A(23..0) to PADD(23..0) FPGA pin (cyclone 4), then PADD(23..0) pins to 256P30 flash A(24..1), isn't it ? note: it could be worse like in Motorola world...)
Then the flash programmer should complete.
Also probably, with your configuration, the programmer inside quartus works well. Only Nios II Flash programmer failed.
Next difficulty is to place configuration data and nios code to the right place in parallel flash which seems not obvious in flash programmer GUI. (version 11, may be not possible to offset correctly configuration data, so should use command line flash programmer)
Hope it can help other people if too late for you...
Regards,
Michelg34