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It did clash. Changing all of the instance names in the project to "inst1" through "instN" cleared the compilation errors.
I'm old school and prefer schematic entry. The arguments in favor of an HDL-based design are uncompelling to many outside the confines of the Altera Forum.
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I also use schematic entry and find they are easy to work with. There is a reason why so many software programs have graphic entry such as Cypress PSOC, Microchip, Labview, Simulink, and even Xlinx all have a graphic programming interface. I think if you are a developer that is doing a full design then using schematics is a good way to show the connectivity of your HDL modules. The big problem in using them in your design is that ModelSim doesn't accept them. So you must convert the .bdf file to HDL using File>Create/Update>Generate HDL Design File from Current File and then add that file to the project and make sure the .bdf is not in your project. With that I can use schematics and able to quickly hand off my design to other engineers and not spend time using VISO or Power Point to document the design. Everyone that I have worked with has used .bdf files. I'm told that Xilinx has a built-in Simulator that accepts the graphical files in Xilinx. Our design team have been using Quartus for so long it would be hard to make the switch to Xilinx. Last, if you are designer that is working on one portion of a design then I can understand using schematic may be a pain but I think the idea that schematics like circuit schematics help show connectivity is very beneficial.
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