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ErenYagar's avatar
ErenYagar
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3 years ago

Error (275033) How to handle multi-bit port connections in Verilog and Quartus?

Hello everyone! Recently, I encountered an issue while designing FPGA circuits using Verilog and Quartus, and I would like to seek your advice. I'm trying to connect a multi-bit port, but during com...
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ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

The bus wire needs to be assigned the name as well (Right-click -> Properties) in your case is A[3..0].

You can leave them unconnected also (check image attached) because they will be connected automatically after compilation, but just make sure those wire naming are matching.

Thanks,

Best Regards,

Sheng

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