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AlexBarry's avatar
AlexBarry
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Error 169182 with Cyclone 10 LP

I am compiling a design for the Cylcone 10 LP (10CL025YE144I7G). We use using active serial configuration mode. Currently, we have a 3.3V LVCMOS output signal on pin 11. When I added the serial fl...
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  • FvM's avatar
    FvM
    2 years ago

    Hi,
    why do you need SFL integrated with application code. Standard solution would be default SFL image loaded by programmer, it doesn't conflict with any application pin assignments.

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,

​

May I know if you have tried to change the I/O standard of that pin to 2.5V?

did the error message still observed?


If yes, then it is likely the same rule happened for the device as well which is to minimizes noise coupling from neighboring I/Os to the DCLK pin.


Regards,

Aqid


AlexBarry's avatar
AlexBarry
Icon for New Contributor rankNew Contributor
2 years ago

We have not tried that, since all of the devices attached to the FPGA will require 3.3V IO. The configuration device is also 3.3V. We do have the option of moving this signal to another pin.

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