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Altera_Forum's avatar
Altera_Forum
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9 years ago

Error (15684)

Hi to all

When compiling a design on EP2C20 I have this error :

Error (15684): M4K memory block WYSIWYG primitive "video:inst9|vdp_vram:U_VRAM|altsyncram:r_rtl_0|altsyncram_1nm1:auto_generated|ram_block1a4" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.

This design compile well on my EP4CE6 but I need more MK4 block.

Files are attached

Someone can help me ?

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    One thing I notice with your code is that you dont register the read address, as is usually required to infer ram in Altera devices. Have you tried registering the addr as recommended?

    Secondly - did you read the errata sheet as suggested?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Probably and old post... but ran into this same problem today.....I think the Error (15684) is related to the use of two clocks when using true dual port RAM.. see https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ds/es_cycii.pdf on page.3.. Ive used the template method to stick the ram in my project then edited the template to drive the ram by the same clock and it seems that the synth passes ok...still testing it

    cheers