New ContributorI'm using Quartus 18.1 and Normal IEEE Libraries (my device is the MAX 10 CPLD). However, when I compile the design it declares the above error during Analysis & Synthesis process. Can anybody tell me what that is and how can I go about resolving the error so it won't repeat? Your help is urgent and appreciated. Thanks, ~Fouad Elayyach
Super ContributorSeem same issue with some discussion. Please take a look.
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