Occasional Contributor
Occasional Contributorhi,
thanks for the reply...
as you said i checked the missing port but there is a port in the qsys....
i am attaching the project here... can you please check and let me knw...
the qsys design is in the RSU floder-> onchip.qsys
Regular ContributorHi,
I will check the project.
Meanwhile can you discard any unused project/previous unused project in your folder, or simply create a clean one in a new folder, see if it works.
Here is a similar discussion regarding the error in case I am late with the update:
https://forums.intel.com/s/question/0D50P000046IjYRSA0/system-verilog-pass-typedef-struct-packed-between-modules-error-12002-port-x-does-not-exist-in-macrofunction-y
Regards.
