Forum Discussion
Hi,
Here are the possible solution for your issue:
- Check the Qsys system to ensure the missing port exists in the design
- If you have duplicates or more than one output folder, please remove the unused output folder, the error might be Qsys confused between the output folders.
Let me know if the problem persist.
- AKAYA6 years ago
Occasional Contributor
hi,
thanks for the reply...
as you said i checked the missing port but there is a port in the qsys....
i am attaching the project here... can you please check and let me knw...
the qsys design is in the RSU floder-> onchip.qsys
- EBERLAZARE_I_Intel6 years ago
Regular Contributor
Hi,
I will check the project.
Meanwhile can you discard any unused project/previous unused project in your folder, or simply create a clean one in a new folder, see if it works.
Here is a similar discussion regarding the error in case I am late with the update:
https://forums.intel.com/s/question/0D50P000046IjYRSA0/system-verilog-pass-typedef-struct-packed-between-modules-error-12002-port-x-does-not-exist-in-macrofunction-y
Regards.
- AKAYA6 years ago
Occasional Contributor
hi,
as per your suggestion i tried deleting all the unwanted folders and comiling it again but still the same problem persist.
can you let me know whatelse can be done
- EBERLAZARE_I_Intel6 years ago
Regular Contributor
Hi,
Are you using MAX10 board? Also, how did you do the design? Is it from a tutorial that you follow or any guides.
Regards.