Error (10477): VHDL error at add_sub.vhd(57): name "add" must represent signal How to solve this error? Thanks.

LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_signed.all; -- Entity Declaration ENTITY add_sub IS PORT ( A,B : IN STD_LOGIC_VECTOR(3 downto 0); SEL : IN STD_LOGIC; S...