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DPate8's avatar
DPate8
Icon for New Contributor rankNew Contributor
7 years ago

Error (10477): VHDL error at add_sub.vhd(57): name "add" must represent signal How to solve this error? Thanks.

LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_signed.all; -- Entity Declaration ENTITY add_sub IS PORT ( A,B : IN STD_LOGIC_VECTOR(3 downto 0); SEL : IN STD_LOGIC; S...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

add and sub are process labels and are illegal assignments. If you want to call them as functions, you will have to declare both add and sub as functions and not processes.