Forum Discussion
DPate8
New Contributor
New ContributorError (10477): VHDL error at add_sub.vhd(57): name "add" must represent signal How to solve this error? Thanks.
LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_signed.all; -- Entity Declaration ENTITY add_sub IS PORT ( A,B : IN STD_LOGIC_VECTOR(3 downto 0); SEL : IN STD_LOGIC; S...
Abe
Frequent Contributor
Frequent Contributoradd and sub are process labels and are illegal assignments. If you want to call them as functions, you will have to declare both add and sub as functions and not processes.
