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Altera_Forum
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12 years ago

Error (10170): Verilog HDL syntax error at CMD_FSM3.sv(109) near text "~&"; expectin

hi all, i'm trying to write FSM that check few commands out of about 10 available command and i get this error message when trying to use nand with if can you please tell me what do i do wrong?...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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~& is not a valid operator in Verilog. For a NAND, you should write it as:

(~((!data_in_valid) && (data_in==GET_CONFIGURATION)))

or

(~((!data_in_valid) & (data_in==GET_CONFIGURATION)))

In this case a long as data_in_valid is a single bit expression both will give the same answer.

Pete

--- Quote End ---

Thank you Pete!