Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorError (10119): Verilog HDL Loop...must terminate within 250 iterations
Hello @all, I have a problem with a Verilog module where I use a for-loop to drive the processesing of a blob detection. The module receives a register which contains the X- and Y-Coordina...
Altera_ForumHonored Contributor
Honored ContributorIn a HDL (hardware definition language), iteration schemes have a different meaning than in procedural programming languages. They don't define sequential processing of the included statements but are a method to define parallel processing. Even if the iteration construct would be accepted by the Veriolog compiler (when using constant loop parameters), the resource requirement would go beyond any meaningful FPGA size.
Interestingly, the 50 MHz clock isn't used at all in your code, but it should be. The only suitable way is to perform the calculation sequentially, one step for each clock cycle.
