EPM CPLD's Internal Osc Frequency

Hi!

I'm working with a EPM570 and need a clock source.

I created it with the block ALTUFM_OSC, set the frequency to 5.5 MHz and checked it worked by simulating the circuit.

As stated in the help file of ALTUFM_OSC, the frequency of 5.5 MHz I've selected it's only "for simulation purpouses and has no impact on the on-chip oscillator frequency".

My question is, what will be the real frequency of the oscillator when I upload the source code to the CPLD? Is it uncertain and will be between 3.3 and 5.5 MHz?

If it's really uncertain and I need a deterministic frequency for the global clock, how can I interface a crystal into the CPLDs pins?

It may have been asked before, but I had no luck finding the answers.

Thanks in advance for your help.