Forum Discussion
Honored ContributorEPCS16 AS Can't Verify Device (General AS Programming Issues)
I have a custom board and the TerasicBlaster (USB Blaster Clone) and at least some communication seems to start OK (reports Device 1 silicon ID is 0x15). I can Erase and Blank Check successfully most of the time (have had a few errors). But when I program and verify it goes through what appears to be the programming process for maybe 15-30 seconds, and then says Can't verify device 1 immediately after trying to starting verification. I'm totally new to this FPGA stuff, and any pointers would be much appreciated!
Thanks! -JNS.13 Replies
Altera_ForumThe FPGA isn't involved in AS programming, the FPGA AS interface is disabled by the USB Blaster or another programmer, as it pulls up the nCE line. AS Programming would be possible without a FPGA assembled to circuit.
But the FPGA can also program AS memory through the interface, this is utilized with said serial flash loader.- Altera_Forum
Thanks for the ideas. I have 10pF on DCLK, but I'll try some different values and experiment with the series R.
How involved is the FPGA in the process during the programming of the configuration device? Is it being programmed simultaneously and signaling back to the usbblaster. Is the Usbblaster trying to verify from the epcs chip or the fpga? Off to do some experimentation. Thanks, -JNS. - Altera_Forum
I expererienced similar behaviour with USB Blaster and a 0.5 m long IDC flat cable that worked correct for JTAG programming. With a regular short cable, AS programming proceeded normally. You are probably using the Terasic USB Blaster with it's original cable, so you have no option to further improve AS signal quality.
You can see however from my experience, that AS programming interface is rather sensitive to signal quality issues, more than JTAG. With Cyclone III, Altera published a suggestion to connect a small capacitor (around 10 pF) at DCLK which apparently improved the situation. Also a small series resistor at DCLK (50 - 100 ohms) may help. I assume, that AS programming connector and EPCS are located near to FPGA and have state-of-the-art wiring, otherwise, the problem could be related mainly to your design. It could be, that although verify fails, the device is programmed correct. If you have also a JTAG interface at the FPGA, you can program the AS device through serial flash loader (SFL) alternatively. SFL works with all FPGAs that also support SignalTap. See the respective application note how to use SFL.
