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Altera_Forum
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18 years agoI expererienced similar behaviour with USB Blaster and a 0.5 m long IDC flat cable that worked correct for JTAG programming. With a regular short cable, AS programming proceeded normally. You are probably using the Terasic USB Blaster with it's original cable, so you have no option to further improve AS signal quality.
You can see however from my experience, that AS programming interface is rather sensitive to signal quality issues, more than JTAG. With Cyclone III, Altera published a suggestion to connect a small capacitor (around 10 pF) at DCLK which apparently improved the situation. Also a small series resistor at DCLK (50 - 100 ohms) may help. I assume, that AS programming connector and EPCS are located near to FPGA and have state-of-the-art wiring, otherwise, the problem could be related mainly to your design. It could be, that although verify fails, the device is programmed correct. If you have also a JTAG interface at the FPGA, you can program the AS device through serial flash loader (SFL) alternatively. SFL works with all FPGAs that also support SignalTap. See the respective application note how to use SFL.