EPCS memory (1MBIT) not response

Hello,

Sorry for my bad English.

I have a problem with communication between ATMEGA128 and EPCS memory (1MBIT).

Result product may be a altera programmer constructed from FTDI-ATMEGA-EPCS.

Memory not responce for any operation code. I try next one:

https://www.alteraforum.com/forum/attachment.php?attachmentid=6491 https://www.alteraforum.com/forum/attachment.php?attachmentid=6492 https://www.alteraforum.com/forum/attachment.php?attachmentid=6493

First image is read status, second image is write enable and third image is write status. This images are from osciloscope measure at real device.

Could anyone help??? Thak you very much

------------------------------------

source code:

main loop:

char registr = 0b00000011;

while(1){

_delay_ms(200);

write_enable();

write_status(registr);

read_status();

}

--------------------------

void write_enable(void){

char intsr = 0b00000110;

PORTD &= ~(1<<NCS); // CLR NCS

_delay_ms(20);

for(int i = 7;i>=0;i--){

_delay_us(3);

PORTD &= ~(1<<DCLK); //clear CLK

_delay_us(1);

if((intsr&(1<<i))!=0){

PORTG |= (1<<ASDI); // setb ASDI

}else {

PORTG &= ~(1<<ASDI);// clr ASDI

}

_delay_us(3);

PORTD |= (1<<DCLK); //data load at rising edge

}

_delay_us(1);

PORTD &= ~(1<<DCLK); //clear clk

_delay_us(3);

PORTD |= (1<<NCS); // SETB NCS

}

-----------------------------------------

void write_status(char registr){

char intsr = 0b00000001;

PORTD &= ~(1<<NCS); // CLR NCS

_delay_ms(20);

for(int i = 7;i>=0;i--){

_delay_us(3);

PORTD &= ~(1<<DCLK); //clear clk

_delay_us(3);

if((intsr&(1<<i))!=0){

PORTG |= (1<<ASDI); // setb ASDI

}else {

PORTG &= ~(1<<ASDI);// clr ASDI

}

_delay_us(3);

PORTD |= (1<<DCLK); //data load at rising edge

}

for(int i = 7;i>=0;i--){

_delay_us(3);

PORTD &= ~(1<<DCLK); //clear CLK

_delay_us(3);

if((registr&(1<<i))!=0){

PORTG |= (1<<ASDI); // setb ASDI

}else {

PORTG &= ~(1<<ASDI);// clr ASDI

}

_delay_us(3);

PORTD |= (1<<DCLK); //data load at rising edge

}

_delay_us(3);

PORTD &= ~(1<<DCLK); //clear clk

_delay_us(3);

PORTD |= (1<<NCS); // SETB NCS

}

------------------------------------

void read_status(void){

char intsr = 0b00000101;

PORTD &= ~(1<<NCS); // CLR NCS

_delay_ms(20);

for(int i = 7;i>=0;i--){

if((intsr&(1<<i))!=0){

PORTG |= (1<<ASDI); // setb ASDI

}else {

PORTG &= ~(1<<ASDI);// clr ASDI

}

_delay_us(3);

PORTD |= (1<<DCLK); //data load at rising edge

_delay_us(3);

PORTD &= ~(1<<DCLK); //clear CLK

_delay_us(3);

}

_delay_us(3);

for(int i = 7;i>=0;i--){

PORTD &= ~(1<<DCLK); //clear CLK

_delay_us(3);

PORTD |= (1<<DCLK); //data load at rising edge

_delay_us(3);

}

PORTD |= (1<<NCS); // SETB NCS

}