EPCS Config via SOPC Builder component in normal user design

Hi,

the problem is that the boards are already there, they lack an external SRAM for NIOS (maybe the FPGA SRAM would suffice but we need it for other stuff, too) and keeping power consumption low on the boards is a very important thing for us. Therefore I don't want to implement a NIOS there only for the purpose of updating the flash, which should happen very infrequently while it will surely degrade the performance of the overall system.

But you think that Quartus will synthesize VHDL only solution?

Best regards,

flintstone