New Contributor
ContributorI'm unaware of any design guidelines specifically for this. Keep things as short as possible and you should realise a working solution. The topology is pretty tolerant and forgiving as far as programming and subsequent configuration is concerned. It'll put up with some generous trace lengths too.
If you're still concerned I recommend you consider JTAG indirect Configuration. This removes any need for T paths in the copper, allowing you to program the EPCS/EPCQ from the FPGA, via JTAG.
Have a look at:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an370.pdf
Cheers,
Alex
