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LD's avatar
LD
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7 years ago

EPCQ-L NVCR Documentation is incorrect

Concern : Intel Premier Support Case 00351159 - EPCQ-L NVCR Documentation is incorrect Hi, It seems that the documentation of the EPCQ-L is not correct (https://www.intel.com/content/dam/altera...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

​Hi LD,

Yes, you are correct. In the EPCQL device, the NVCR bit[4] is defaulted to 1. The Quartus Prime programmer and active serial configuration don't use RESET or HOLD function, thus the bit[4] is set to 0. Users are recommend to set this bit[4] to 0 to disable RESET or HOLD function on DQ3 pin.

Regards,

Nooraini