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lipingx's avatar
lipingx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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EP4CE15U14A7N DDR2 interface

Use bank 2, 3, 4 for ddr2: micron MT47H128M16RT-25E:C TR question: 1) only 1 DQS pin marked in pin list, how to handle LDQS and UDOS? 2) The DDR2 DQS pin is differential, but FPGA is single end, h...
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  • FvM's avatar
    FvM
    2 years ago

    Hi,

    just read the device manual and pin list thoroughly.

    Post #1 is quoting the DQS for x16/x18 column, however as clearly written in the device manual and stated in post #2, DDR2 RAM has to use x8/x9 DQS configuration. There are more DQS pins available for x8/x9, e.g. M7 and T7 in bottom banks B3/B4.

lipingx's avatar
lipingx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

talk more on it:

Then the only choice to get 16 bit done are to use bank 3 and bank 8 together, but one bank located at top side, the other bank located at bottom side. I am not sure if it's the right way. Generally they should be located nearby bank for one ddr chip.

if I assigned bank3 and bank 4 as ddr and there are still some free 1.8V IO not used, can I assign the free IO for other function?

For example: some bank3 IO are assigned to ddr, some bank3 IO are assigned to spi, general input and output.

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